CXL 3.0

Compute Express Link 3.0 — the third-generation specification (published February 2026) that extends PCIe capabilities to create **rack-scale, coherent memory fabrics**. CXL 3.0 facilitates dynamic memory pooling, allowing multiple independent hosts to share a single block of memory via specialized switching fabrics. Distributed Page Caches (DPC) over CXL.mem treat the entire cluster's main memory as a single cache budget, enforcing a single-copy invariant via CXL-based remote mappings. As CXL-attached NVMe SSDs and byte-addressable persistent memory mature, the strict delineation between host RAM and object storage dissolves — AI workflows increasingly use CXL.mem to access shared vector indices and KV-caches.

Traditional per-node page caches replicate hot data locally and waste aggregate cluster DRAM. AI workloads at scale need a coherent memory abstraction that treats DRAM across the rack as a single shared resource. CXL 3.0's coherency protocol makes this possible without the application-layer overhead of distributed-key-value-store coordination. The strategic shift: shared vector indices and KV-caches no longer need to be serialized to network S3 endpoints for cross-host visibility — CXL.mem provides byte-addressable access to remote memory pools at sub-microsecond latency.

Distributed Page Caches (DPC), rack-scale coherent vector indices, shared KV-cache fabrics across inference clusters, byte-addressable persistent memory for AI agent state, CXL-attached NVMe expansion for tier-3.5 storage.